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rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a dual bipolar/jfet, audio operational amplifier OP275* pin connections 8-lead narrow-body so 8-lead epoxy dip (s suffix) (p suffix) OP275 out a ?n a +in a v out b ?n b +in b v+ 1 2 3 4 5 6 7 8 1 2 3 4 8 7 6 5 OP275 out b ?n b +in b v+ out a ?n a +in a v improved dc performance is also provided with bias and offset currents greatly reduced over purely bipolar designs. input off- set voltage is guaranteed at 1 mv and is typically less than 200 m v. this allows the OP275 to be used in many dc coupled or summing applications without the need for special selections or the added noise of additional offset adjustment circuitry. the output is capable of driving 600 w loads to 10 v rms while maintaining low distortion. thd + noise at 3 v rms is a low 0.0006%. the OP275 is specified over the extended industrial (C40 c to +85 c) temperature range. OP275s are available in both plastic dip and soic-8 packages. soic-8 packages are available in 2500 piece reels. many audio amplifiers are not offered in soic-8 surface mount packages for a variety of reasons; how- ever, the OP275 was designed so that it would offer full perfor- mance in surface mount packaging. general description the OP275 is the first amplifier to feature the butler amplifier front-end. this new front-end design combines both bipolar and jfet transistors to attain amplifiers with the accuracy and low noise performance of bipolar transistors, and the speed and sound quality of jfets. total harmonic distortion plus noise equals that of previous audio amplifiers, but at much lower sup- ply currents. a very low l/f corner of below 6 hz maintains a flat noise density response. whether noise is measured at either 30 hz or 1 khz, it is only 6 nv/ ? hz . the jfet portion of the input stage gives the OP275 its high slew rates to keep distortion low, even when large output swings are required, and the 22 v/ m s slew rate of the OP275 is the fastest of any standard audio amplifier. best of all, this low noise and high speed are accomplished using less than 5 ma of supply current, lower than any standard audio amplifier. * protected by u.s. patent no. 5,101,126. ? analog devices, inc., 1995 one technology way, p.o. box 9106, norwood. ma 02062-9106, u.s.a. tel: 617/329-4700 fax: 617/326-8703 features excellent sonic characteristics low noise: 6 nv/ ? hz low distortion: 0.0006% high slew rate: 22 v/ m s wide bandwidth: 9 mhz low supply current: 5 ma low offset voltage: 1 mv low offset current: 2 na unity gain stable soic-8 package applications high performance audio active filters fast amplifiers integrators
electrical characteristics parameter symbol conditions min typ max units audio performance thd + noise v in = 3 v rms, r l = 2 k w , f = 1 khz 0.006 % voltage noise density e n f = 30 hz 7 nv/ ? hz f = 1 khz 6 nv/ ? hz current noise density i n f = 1 khz 1.5 pa/ ? hz headroom thd + noise 0.01%, r l = 2 k w , v s = 18 v >12.9 dbu input characteristics offset voltage v os 1mv C40 c t a +85 c 1.25 mv input bias current i b v cm = 0 v 100 350 na v cm = 0 v, C40 c t a +85 c 100 400 na input offset current i os v cm = 0 v 2 50 na v cm = 0 v, C40 c t a +85 c 2 100 na input voltage range v cm C10.5 +10.5 v common-mode rejection ratio cmrr v cm = 10.5 v, C40 c t a +85 c 80 106 db large signal voltage gain a vo r l = 2 k w 250 v/mv r l = 2 k w , C40 c t a +85 c 175 v/mv r l = 600 w 200 v/mv offset voltage drift d v os / d t2 m v/ c output characteristics output voltage swing v o r l = 2 k w C13.5 13.9 +13.5 v r l = 2 k w , C40 c t a +85 c C13 13.9 +13 v r l = 600 w , v s = 18 v +14, C16 v power supply power supply rejection ratio psrr v s = 4.5 v to 18 v 85 111 db v s = 4.5 v to 18 v, C40 c t a +85 c80 db supply current i sy v s = 4.5 v to 18 v, v o = 0 v, r l = , C40 c t a +85 c45ma v s = 22 v, v o = 0 v, r l = , C40 c t a +85 c 5.5 ma supply voltage range v s 4.5 22 v dynamic performance slew rate sr r l = 2 k w 15 22 v/ m s full-power bandwidth bw p khz gain bandwidth product gbp 9 mhz phase margin ? m 62 degrees overshoot factor v in = 100 mv, a v = +1, r l = 600 w , c l = 100 pf 10 % specifications subject to change without notice. rev. a C2C OP275Cspecifications (@ v s = 6 15.0 v, t a = +25 8 c unless otherwise noted)
OP275 rev. a C3C parameter symbol conditions limit units offset voltage v os 1mv max input bias current i b v cm = 0 v 350 na max input offset current i os v cm = 0 v 50 na max input voltage range 1 v cm 10.5 v min common-mode rejection ratio cmrr v cm = 10.5 v 80 db min power supply rejection ratio psrr v = 4.5 v to 18 v 85 db min large signal voltage gain a vo r l = 2 k w 250 v/mv min output voltage range v o r l = 10 k w 13.5 v min supply current i sy v o = 0 v, r l = 5 ma max notes electrical tests and wafer probe to the limits shown. due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard product dice. consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and test ing. 1 guaranteed by cmrr test. specifications subject to change without notice. wafer test limits (@ v s = 6 15.0 v, t a = +25 8 c unless otherwise noted) absolute maximum ratings 1 supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 v input voltage 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 v differential input voltage 2 . . . . . . . . . . . . . . . . . . . . . . . 7.5 v output short-circuit duration to gnd 3 . . . . . . . . . indefinite storage temperature range p, s package . . . . . . . . . . . . . . . . . . . . . . . . C65 c to +150 c operating temperature range OP275g . . . . . . . . . . . . . . . . . . . . . . . . . . . . C40 c to +85 c junction temperature range p, s package . . . . . . . . . . . . . . . . . . . . . . . . C65 c to +150 c lead temperature range (soldering, 60 sec) . . . . . . . +300 c package type q ja 4 q jc units 8-pin plastic dip (p) 103 43 c/w 8-pin soic (s) 158 43 c/w notes 1 absolute maximum ratings apply to both dice and packaged parts, unless otherwise noted. 2 for supply voltages greater than 22 v, the absolute maximum input voltage is equal to the supply voltage. 3 shorts to either supply may destroy the device. see data sheet for full details. 4 q ja is specified for the worst case conditions, i.e., q ja is specified for device in socket for cerdip, p-dip, and lcc packages; q ja is specified for device soldered in circuit board for soic package. warning! esd sensitive device caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the OP275 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. ordering guide model temperature range package option OP275gp C40 c to +85 c 8-pin plastic dip OP275gs C40 c to +85 c 8-pin soic OP275gsr C40 c to +85 c so-8 reel, 2500 pcs. OP275gbc +25 c dice dice characteristics die size 0.070 0.108 in. (7,560 sq. mils) substrate is connected to vC
OP275Ctypical performance curves rev. a C4C supply voltage ?v output voltage swing ?v 25 20 ?5 0 5 25 10 15 20 ? ?0 ?5 ?0 15 5 10 0 t a = +25 c r l = 2k w +vom ?om output voltage swing vs. supply voltage frequency ?hz 1m 10m 10k 100k phase ?degrees 135 90 45 0 ?5 ?0 60 50 ?0 40 30 20 10 0 ?0 gain ?db v s = 15v t a = +25 c marker 15 309.059hz mag (a/h) 60.115db marker 15 309.058hz phase (a/r 90.606deg open-loop gain, phase vs. frequency frequency ?hz 120 100 0 100 1k 10m 10k 100k 1m 80 60 40 20 v s = 15v t a = +25 c common-mode rejection ?db common-mode rejection vs. frequency temperature ? c open-loop gain ?v/mv 1500 0 ?0 ?5 100 0255075 1250 1000 750 500 250 v s = 15v v o = 10v +gain r l = 2k w ?ain r l = 2k w +gain r l = 600 w ?ain r l = 600 w open-loop gain vs. temperature frequency ?hz 50 closed-loop gain ?db 40 ?0 1k 10k 100m 100k 1m 10m 30 20 10 0 ?0 ?0 v s = 15v t a = +25 c a vcl = +100 a vcl = +10 a vcl = +1 closed-loop gain vs. frequency frequency ?hz 120 100 0 10 100 1m 1k 10k 100k 80 60 40 20 power supply rejection ?db v s = 15v t a = +25 c +psrr ?srr power supply rejection vs. frequency frequency ?hz 1m 10m 10k 100k phase ?degrees 180 135 ?80 90 45 0 ?5 ?0 ?35 40 30 ?0 20 10 0 ?0 ?0 ?0 gain ?db v s = 15v t a = +25 c closed-loop gain and phase, a v = +1 frequency ?hz 60 impedance ? w 50 0 100 1k 10m 10k 100k 1m 40 30 20 10 v s = 15v t a = +25 c a vcl = +1 a vcl = +10 a vcl = +100 closed-loop output impedance vs. frequency frequency ?hz 100 80 ?0 1k 10k 100m 100k 1m 10m 60 40 20 0 ?0 ?0 0 phase ?degrees 45 90 135 180 225 270 v s = 15v r l = 2k w t a = +25 c open-loop gain ?db gain phase m = 58 open-loop gain, phase vs. frequency
OP275 rev. a C5C load capacitance ?pf 100 overshoot ?% 90 0 0 100 500 200 300 400 40 30 20 10 80 60 70 50 a vcl = +1 negative edge a vcl = +1 positive edge v s = 15v r l = 2k w v in = 100mv p-p small-signal overshoot vs. load capacitance supply voltage ?v 5.0 supply current ?ma 4.5 3.0 0 5 25 10 15 4.0 3.5 20 t a = +25 c t a = ?0 c t a = +85 c supply current vs. supply voltage frequency ?hz 10 100 100k 1k 5 4 3 2 1 current noise density ?pa/ hz v = 15v t = +25 c s a current noise density vs. frequency 16 8 0 100 1k 10k 2 4 6 10 12 14 load resistance ? w t a = +25 c v s = 15v +vom ? ?om ? maximum output swing ?v maximum output voltage vs. load resistance temperature ? c absolute output current ?ma 120 20 ?0 ?5 100 0255075 110 70 60 50 30 100 90 80 40 v s = 15v sink source short circuit current vs. temperature tcv os ?/ c units 500 400 0 01 10 23 4 5 67 8 9 300 200 100 based on 920 op amps v s = 15v ?0 c to +85 c tcv os distribution temperature ? c gain bandwidth product ?mhz 11 10 7 ?0 ?5 100 0255075 9 8 phase margin ?degrees 65 60 40 55 50 gbw m gain bandwidth product, phase margin vs. temperature 25 20 15 10 5 frequency ?hz maximum output swing ?v 30 0 1k 10k 10m 100k 1m t a = +25 c v s = 15v a vcl = +1 r l = 2k w maximum output swing vs. frequency temperature ? c 300 input bias current ?na 0 ?0 ?5 100 0255075 250 200 150 100 50 v s = 15v input bias current vs. temperature
input offset voltage ?? units 200 160 0 ?00 ?00 500 ?00?00 ?00 0 100 200 300 400 120 80 40 based on 920 op amps v s = 15v t a = +25 c input offset (v os ) distribution settling time ?ns step size ?v 10 8 ?0 ? ? ? ? 6 2 4 0 0 100 900 200 300 400 500 600 700 800 +0.1% +0.01% ?.1% ?.01% settling time vs. step size +sr ?r capacitive load ?pf 50 45 slew rate ? v/? 20 0 100 500 200 300 400 40 35 30 25 t a = +25 c v s = 15v slew rate vs. capacitive load 10 0% 100 90 200ns 5v negative slew rate r l = 2 k w , v s = 15 v, a v = +1 10 0% 100 90 100ns 50mv small signal response r l = 2 k w , v s = 15 v, a v = +1 10 0% 100 90 200ns 5v positive slew rate r l = 2 k w , v s = 15 v, a v = +1 2.5 khz 0 hz ch a: 80.0 ? fs 10.0 ?/div mkr: 6.23 nv/ ? hz bw: 15.0 mhz mkr: 1 000 hz voltage noise density vs. frequency v s = 15 v OP275Ctypical performance curves rev. a C6C differential input voltage ?v 40 20 0 0.2.4.6.81.0 35 30 10 5 25 15 slew rate ?v/? v s = 15v r l = 2k w t a = +25 c slew rate vs. differential input voltage temperature ? c 50 slew rate ?v/? 20 ?0 ?5 100 0255075 45 40 35 30 25 ?r +sr v s = 15v r l = 2k w slew rate vs. temperature
OP275 rev. a C7C applications short circuit protection the OP275 has been designed with inherent short circuit pro- tection to ground. an internal 30 w resistor, in series with the output, limits the output current at room temperature to i sc + = 40 ma and i sc C = C90 ma, typically, with 15 v supplies. however, shorts to either supply may destroy the device when excessive voltages or currents are applied. if it is possible for a user to short an output to a supply, for safe operation, the out- put current of the OP275 should be design-limited to 30 ma, as shown in figure 1. total harmonic distortion total harmonic distortion + noise (thd + n) of the OP275 is well below 0.001% with any load down to 600 w . however, this is dependent upon the peak output swing. in figure 2 it is seen that the thd + noise with 3 v rms output is below 0.001%. in the following figure 3, thd + noise is below 0.001% for the 10 k w and 2 k w loads but increases to above 0.1% for the 600 w load condition. this is a result of the output swing capability of the OP275. notice the results in figure 4, showing thd vs. v in (v rms). this figure shows that the thd + noise remains very low until the output reaches 9.5 volts rms. this performance is similar to competitive products. r fb feedback r x 332 w a1 v out a1 = 1/2 OP275 figure 1. recommended output short circuit protection r l = 600 w , 2k, 10k v s = 15v v in = 3v rms a v = +1 0.010 0.001 0.0005 20 100 1k 10k 20k frequency ?hz thd + noise ?% figure 2. thd + noise vs. frequency vs. r load 1 0.001 0.0001 20 100 1k 10k 20k thd + noise ?% frequency ?hz a v = +1 v s = 18v v in = 10v rms 80khz filter 600 w 2k 10k 0.1 0.010 figure 3. thd + noise vs. r load ; v in =10 v rms, 18 v supplies v s = 18v r l = 600 w 0.010 0.001 0.0001 0.5 1 10 thd + noise ?% output swing ?v rms figure 4. headroom, thd + noise vs. output amplitude (v rms); r load = 600 w , v sup = 18 v the output of the OP275 is designed to maintain low harmonic distortion while driving 600 w loads. however, driving 600 w loads with very high output swings results in higher distortion if clipping occurs. a common example of this is in attempting to drive 10 v rms into any load with 15 volt supplies. clipping will occur and distortion will be very high. to attain low harmonic distortion with large output swings, supply voltages may be increased. figure 5 shows the perfor- mance of the OP275 driving 600 w loads with supply voltages varying from 18 volts to 20 volts. notice that with 18 volt supplies the distortion is fairly high, while with 20 volt supplies it is a very low 0.0007%. supply voltage ?v 0.0001 0.001 thd ?% 0 17 22 18 19 20 21 0.01 0.1 r l = 600 w v out = 10 vrms @ 1khz figure 5. thd + noise vs. supply voltage noise the voltage noise density of the OP275 is below 7 nv/ ? hz from 30 hz. this enables low noise designs to have good perfor- mance throughout the full audio range. figure 6 shows a typical OP275 with a 1/f corner at 2.24 hz. 10 hz 0 hz ch a: 80.0 ? fs 10.0 ?/div mkr: 45.6 ?/ ? hz bw: 0.145 hz mkr: 2.24 hz figure 6. 1/f noise corner, v s = 15 v, a v = 1000
OP275 rev. a C8C noise testing for audio applications the noise density is usually the most im- portant noise parameter. for characterization the OP275 is tested using an audio precision, system one. the input signal to the audio precision must be amplified enough to measure it accurately. for the OP275 the noise is gained by approximately 1020 using the circuit shown in figure 7. any readings on the audio precision must then be divided by the gain. in imple- menting this test fixture, good supply bypassing is essential. a b OP275 909 w 100 w op37 909 w 100 w 909 w 100 w op37 4.42k w 490 w output figure 7. noise test fixture input overcurrent protection the maximum input differential voltage that can be applied to the OP275 is determined by a pair of internal zener diodes con- nected across its inputs. they limit the maximum differential in- put voltage to 7.5 v. this is to prevent emitter-base junction breakdown from occurring in the input stage of the OP275 when very large differential voltages are applied. however, in or- der to preserve the OP275s low input noise voltage, internal re- sistances in series with the inputs were not used to limit the current in the clamp diodes. in small signal applications, this is not an issue; however, in applications where large differential voltages can be inadvertently applied to the device, large tran- sient currents can flow through these diodes. although these di- odes have been designed to carry a current of 5 ma, external resistors as shown in figure 8 should be used in the event that the OP275s differential voltage were to exceed 7.5 v. OP275 1.4k w 1.4k w + 2 3 6 figure 8. input overcurrent protection output voltage phase reversal since the OP275s input stage combines bipolar transistors for low noise and p-channel jfets for high speed performance, the output voltage of the OP275 may exhibit phase reversal if either of its inputs exceed its negative common-mode input voltage. this might occur in very severe industrial applications where a sensor, or system, fault might apply very large voltages on the inputs of the OP275. even though the input voltage range of the OP275 is 10.5 v, an input voltage of approximately C13.5 v will cause output voltage phase reversal. in inverting amplifier configurations, the OP275s internal 7.5 v input clamping di- odes will prevent phase reversal; however, they will not prevent this effect from occurring in noninverting applications. for these applications, the fix is a simple one and is illustrated in figure 9. a 3.92 k w resistor in series with the noninverting input of the OP275 cures the problem. r fb* v in r s 3.92k w v out r l 2k w *r fb is optional figure 9. output voltage phase reversal fix overload, or overdrive, recovery overload, or overdrive, recovery time of an operational amplifier is the time required for the output voltage to recover to a rated output voltage from a saturated condition. this recovery time is important in applications where the amplifier must recover quickly after a large abnormal transient event. the circuit shown in figure 10 was used to evaluate the OP275s overload recovery time. the OP275 takes approximately 1.2 m s to recover to v out = +10 v and approximately 1.5 m s to recover to v out = C10 v. v in r s 909 w v out r l 2.43k w a1 = 1/2 OP275 r2 10k w r1 1k w 4v p-p @100hz 1 2 3 a1 figure 10. overload recovery time test circuit measuring settling time the design of OP275 combines high slew rate and wide gain- bandwidth product to produce a fast-settling (t s < 1 m s) ampli- fier for 8- and 12-bit applications. the test circuit designed to measure the settling time of the OP275 is shown in figure 11. this test method has advantages over false-sum node tech- niques in that the actual output of the amplifier is measured, in- stead of an error voltage at the sum node. common-mode settling effects are exercised in this circuit in addition to the slew rate and bandwidth effects measured by the false-sum-node method. of course, a reasonably flat-top pulse is required as the stimulus. the output waveform of the OP275 under test is clamped by schottky diodes and buffered by the jfet source follower. the signal is amplified by a factor of ten by the op260 and then schottky-clamped at the output to prevent overloading the oscilloscopes input amplifier. the op41 is configured as a fast integrator which provides overall dc offset nulling. high speed operation as with most high speed amplifiers, care should be taken with supply decoupling, lead dress, and component placement. rec- ommended circuit configurations for inverting and noninverting applications are shown in figures 12 and figure 13.
OP275 rev. a C9C +15v + 0.1? 2 3 8 1 4 v in v out r l 2k w ?5v 10? 0.1? 1/2 OP275 10? + figure 12. unity gain follower 0.1? +15v + 10? 2 3 8 1 4 v in v out 2k w ?5v 10? 0.1? 10pf 4.99k w 2.49k w 4.99k w + 1/2 OP275 figure 13. unity gain inverter in inverting and noninverting applications, the feedback resis- tance forms a pole with the source resistance and capacitance (r s and c s ) and the OP275s input capacitance (c in ), as shown in figure 14. with r s and r f in the kilohm range, this pole can create excess phase shift and even oscillation. a small capacitor, c fb , in parallel and r fb eliminates this problem. by setting r s (c s + c in ) = r fb c fb , the effect of the feedback pole is com- pletely removed. r fb c in r s c s c fb v out figure 14. compensating the feedback pole attention to source impedances minimizes distortion since the OP275 is a very low distortion amplifier, careful atten- tion should be given to source impedances seen by both inputs. as with many fet-type amplifiers, the p-channel jfets in the OP275s input stage exhibit a gate-to-source capacitance that varies with the applied input voltage. in an inverting configura- tion, the inverting input is held at a virtual ground and, as such, does not vary with input voltage. thus, since the gate-to-source voltage is constant, there is no distortion due to input capaci- tance modulation. in noninverting applications, however, the gate-to-source voltage is not constant. the resulting capacitance modulation can cause distortion above 1 khz if the input im- pedance is > 2 k w and unbalanced. figure 15 shows some guidelines for maximizing the distortion performance of the OP275 in noninverting applications. the best way to prevent unwanted distortion is to ensure that the parallel combination of the feedback and gain setting resistors (r f and r g ) is less than 2 k w . keeping the values of these resis- tors small has the added benefits of reducing the thermal noise 0p275 v in v out r f r g r s* * r s = r g //r f if r g //r f > 2k w for minimum distortion figure 15. balanced input impedance to minimize distortion in noninverting amplifier circuits 16?0v 0.1? v+ 5v r l 1k w d1 d2 +15v 2n4416 1k w d3 d4 output (to scope) 1? 10k w ic2 r f 2k w 750 w 2n2222a 15k w ?5v 1n4148 dut 1/2 op260aj 16?0v 0.1? 10k w ? + schottky diodes d1?4 are hewlett-packard hp5082-2835 ic1 is 1/2 op260aj ic2 is pmi op41ej v r g 222 w figure 11. OP275s settling time test fixture
OP275 rev. a C10C importance. like the transformer based design, either output can be shorted to ground for unbalanced line driver applications without changing the circuit gain of 1. other circuit gains can be set according to the equation in the diagram. this allows the design to be easily set to noninverting, inverting, or differential operation. a 3-pole, 40 khz low-pass filter the closely matched and uniform ac characteristics of the OP275 make it ideal for use in gic (generalized impedance converter) and fdnr (frequency-dependent negative resis- tor) filter applications. the circuit in figure 18 illustrates a lin- ear-phase, 3-pole, 40 khz low-pass filter using an OP275 as an inductance simulator (gyrator). the circuit uses one OP275 (a2 and a3) for the fdnr and one OP275 (a1 and a4) as an input buffer and bias current source for a3. amplifier a4 is config- ured in a gain of 2 to set the pass band magnitude response to 0 db. the benefits of this filter topology over classical ap- proaches are that the op amp used in the fdnr is not in the signal path and that the filters performance is relatively insensi- tive to component variations. also, the configuration is such that large signal levels can be handled without overloading any of the the filters internal nodes. as shown in figure 19, the OP275s symmetric slew rate and low distortion produce a clean, well- behaved transient response. v in 3 2 1 a1 r1 95.3k w r2 787 w c1 2200pf c2 2200pf r3 1.82k w c3 2200pf r4 1.87k w r5 1.82k w a2 1 2 3 5 6 7 a3 r6 4.12k w c4 2200pf r7 100k w 5 6 7 a4 r8 1k w r9 1k w v out a1, a4 = 1/2 OP275 a2, a3 = 1/2 OP275 figure 18. a 3-pole, 40 khz low-pass filter v out 10vp-p 10khz scale: vertical?v/ div horizontal?0?/ div 10 0% 100 90 figure 19. low-pass filter transient response of the circuit and dc offset errors. if the parallel combination of r f and r g is larger than 2 k w , then an additional resistor, r s , should be used in series with the noninverting input. the value of r s is determined by the parallel combination of r f and r g to maintain the low distortion performance of the OP275. driving capacitive loads the OP275 was designed to drive both resistive loads to 600 w and capacitive loads of over 1000 pf and maintain stability. while there is a degradation in bandwidth when driving capaci- tive loads, the designer need not worry about device stability. the graph in figure 16 shows the 0 db bandwidth of the OP275 with capacitive loads from 10 pf to 1000 pf. 10 9 8 7 6 5 4 3 2 1 0 0 200 400 600 800 1000 c load ?pf bandwidth ?mhz figure 16. bandwidth vs. c load high speed, low noise differential line driver the circuit of figure 17 is a unique line driver widely used in industrial applications. with 18 v supplies, the line driver can deliver a differential signal of 30 v p-p into a 2.5 k w load. the high slew rate and wide bandwidth of the OP275 combine to yield a full power bandwidth of 130 khz while the low noise front end produces a referred-to-input noise voltage spectral density of 10 nv/ ? hz . 1 2 3 a2 1 3 2 a1 5 6 7 a3 v in v o1 v o2 r3 2k r9 50 r11 1k p1 10k r12 1k r10 50 r8 2k r2 2k r5 2k r4 2k r1 2k r7 2k v o2 ?v o1 = v in a1 = 1/2 OP275 a2, a3 = 1/2 OP275 gain = set r2, r4, r5 = r1 and r6, r7, r8 = r3 r3 r1 r6 2k figure 17. high speed, low noise differential line driver the design is a transformerless, balanced transmission system where output common-mode rejection of noise is of paramount
OP275 rev. a C11C OP275 spice model * * node assignments * noninverting input * inverting input * positive supply * negative supply * output * * .subckt OP275 1 2 99 50 34 * * input stage & pole at 100 mhz * r3 5 51 2.188 r4 6 51 2.188 cin 1 2 3.7e-12 cm1 1 98 7.5e-12 cm2 2 98 7.5e-12 c2 5 6 364e-12 i1 97 4 100e-3 ios 1 2 1e-9 eos 9 3 poly(1) 26 28 0.5e-3 1 q1 5 2 7 qx q2 6 9 8 qx r5 7 4 1.672 r6 8 4 1.672 d1 2 36 dz d2 1 36 dz en 3 1 10 0 1 gn1 0 2 13 0 1e-3 gn2 0 1 16 0 1e-3 * eref 98 0 28 0 1 ep 97 0 99 0 1 em 51 0 50 0 1 * * voltage noise source * dn1 35 10 den dn2 10 11 den vn1 35 0 dc 2 vn2 0 11 dc 2 * * current noise source * dn3 12 13 din dn4 13 14 din vn3 12 0 dc 2 vn4 0 14 dc 2 * * current noise source * dn5 15 16 din dn6 16 17 din vn5 15 0 dc 2 vn6 0 17 dc 2 * * gain stage & dominant pole at 32 hz * r7 18 98 1.09e6 c3 18 98 4.55e-9 g1 98 18 5 6 4.57e-1 v2 97 19 1.35 v3 20 51 1.35 d3 18 19 dx d4 20 18 dx * * pole/zero pair at 1.5 mhz/2.7 mhz * r8 21 98 1e-3 r9 21 22 1.25e-3 c4 22 98 47.2e-12 g2 98 21 18 28 1e-3 * * pole at 100 mhz * r10 23 98 1 c5 23 98 1.59e-9 g3 98 23 21 28 1 * * pole at 100 mhz * r11 24 98 1 c6 24 98 1.59e-9 g4 98 24 23 28 1 * * common-mode gain network with zero at 1 khz * r12 25 26 1e6 c7 25 26 1.5915e-12 r13 26 98 1 e2 25 98 poly(2) 1 98 2 98 0 2.50 2.50 * * pole at 100 mhz * r14 27 98 1 c8 27 98 1.59e-9 g5 98 27 24 28 1 * * output stage * r15 28 99 100e3 r16 28 50 100e3 c9 28 50 1e-6 isy 99 50 1.85e-3 r17 29 99 100 r18 29 50 100 l2 29 34 1e-9 g6 32 50 27 29 10e-3 g7 33 50 29 27 10e-3 g8 29 99 99 27 10e-3 g9 50 29 27 50 10e-3 v4 30 29 1.3 v5 29 31 3.8 f1 29 0 v4 1 f2 0 29 v5 1 d5 27 30 dx d6 31 27 dx d7 99 32 dx d8 99 33 dx d9 50 32 dy d10 50 33 dy * * models used * .model qx pnp(bf=5e5) .model dx d(is=1e-12) .model dy d(is=1e-15 bv=50) .model dz d(is=1e-15 bv=7.0) .model den d(is=1e-12 rs=4.35k kf=1.95e-15 af=1) .model din d(is=1e-12 rs=268 kf=1.08e-15 af=1) .ends
OP275 rev. a C12C printed in u.s.a. outline dimensions dimensions shown in inches and (mm). 8-lead narrow-body soic (s suffix) 85 4 1 0.1968 (5.00) 0.1890 (4.80) pin 1 0.1574 (4.00) 0.1497 (3.80) 0.2440 (6.20) 0.2284 (5.80) seating plane 0.0098 (0.25) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.0688 (1.75) 0.0532 (1.35) 0.0500 (1.27) bsc 0.0098 (0.25) 0.0075 (0.19) 0.0500 (1.27) 0.0160 (0.41) 8 0 0.0196 (0.50) 0.0099 (0.25) x 45 8-lead epoxy dip (p suffix) 8 14 5 0.430 (10.92) 0.348 (8.84) 0.280 (7.11) 0.240 (6.10) pin 1 seating plane 0.022 (0.558) 0.014 (0.356) 0.060 (1.52) 0.015 (0.38) 0.210 (5.33) max 0.130 (3.30) min 0.070 (1.77) 0.045 (1.15) 0.100 (2.54) bsc 0.160 (4.06) 0.115 (2.93) 0.325 (8.25) 0.300 (7.62) 0.015 (0.381) 0.008 (0.204) 0.195 (4.95) 0.115 (2.93) c1652aC2C7/95

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